Semiconductor component and method of operation

ABSTRACT

A semiconductor component includes a semiconductor substrate ( 110 ) having first and second portions ( 111, 112 ) with a first conductivity type, a transistor ( 120 ) at least partially located in the semiconductor substrate, and a switching circuit ( 150, 350, 650, 850 ). The transistor includes (i) a first doped region in the first portion of the semiconductor substrate and having the first conductivity type (ii) a terminal, which includes a second doped region having a second conductivity type and located in the first portion of the semiconductor substrate and over the first doped region, and (iii) a third doped region having the second conductivity type and located in the semiconductor substrate below the first portion of the semiconductor substrate and above the second portion of the semiconductor substrate. The switching circuit is electrically coupled to the third doped region to adjust the bias of the third doped region.

FIELD OF THE INVENTION

This invention relates to electronics, in general, and to semiconductorcomponents and methods of operation, in particular.

BACKGROUND OF THE INVENTION

Different types of semiconductor components are often used in automotiveand other high voltage applications. These different types ofsemiconductor components include discrete devices and integratedcircuits. As an example, the discrete devices can be powerMetal-Oxide-Semiconductor (MOS) transistors having source, gate, anddrain terminals. These different types of semiconductor components havebeen combined onto a single semiconductor chip to reduce the cost andspace required for the semiconductor components.

One significant problem of these combined semiconductor componentsoccurs when the drain terminal of the power MOS transistor is forwardbiased. The forward biasing of the drain terminal injects minoritycarriers into the semiconductor substrate, and the minority carriersdegrade the performance of the integrated circuit or circuits located onthe same semiconductor chip.

Several prior attempts have been made to either contain the injectedminority carriers or suppress the injection of minority carriers. Theseprior attempts, however, still have disadvantages of low drain-to-sourcebreakdown voltage, large epitaxial semiconductor layer thickness, and/ornon-isolated power transistors.

Accordingly, a need exists for a semiconductor component with a powertransistor combined with an integrated circuit onto a singlesemiconductor chip where the power transistor has a high drain-to-sourcebreakdown voltage and is isolated from the integrated circuit. A needalso exists for the epitaxial semiconductor layer, in which the powerdevice and the integrated circuit are formed, to have a small thickness.A further need exists for a method of operating a semiconductorcomponent to suppress the injection of minority carriers into thesemiconductor substrate.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention will be better understood from a reading of the followingdetailed description, taken in conjunction with the accompanying figuresin the drawings in which:

FIG. 1 illustrates a partially schematic, cross-sectional view of asemiconductor component in accordance with an embodiment of theinvention;

FIG. 2 illustrates a cross-sectional view of an embodiment of thesemiconductor component of FIG. 1 in accordance with an embodiment ofthe invention;

FIG. 3 illustrates a partially schematic, cross-sectional view of asemiconductor component in accordance with an embodiment of theinvention;

FIG. 4 illustrates a cross-sectional view of a first embodiment of thesemiconductor component of FIG. 3 in accordance with an embodiment ofthe invention;

FIG. 5 illustrates a cross-sectional view of a second embodiment of thesemiconductor component of FIG. 3 in accordance with an embodiment ofthe invention;

FIG. 6 illustrates a partially schematic, cross-sectional view of asemiconductor component in accordance with an embodiment of theinvention;

FIG. 7 illustrates a cross-sectional view of an embodiment of thesemiconductor component of FIG. 6 in accordance with an embodiment ofthe invention;

FIG. 8 illustrates a partially schematic, cross-sectional view of asemiconductor component in accordance with an embodiment of theinvention;

FIG. 9 illustrates a cross-sectional view of an embodiment of thesemiconductor component of FIG. 8 in accordance with an embodiment ofthe invention; and

FIG. 10 illustrates a flow chart of a method of operating asemiconductor component in accordance with an embodiment of theinvention.

For simplicity and clarity of illustration, the drawing figuresillustrate the general manner of construction, and descriptions anddetails of well-known features and techniques are omitted to avoidunnecessarily obscuring the invention. Additionally, elements in thedrawing figures are not necessarily drawn to scale. For example, thedimensions of some of the elements in the figures may be exaggeratedrelative to other elements to help to improve understanding ofembodiments of the present invention. Furthermore, the same referencenumerals in different figures denote the same elements.

Furthermore, the terms first, second, third, and the like in thedescription and in the claims, if any, are used for distinguishingbetween similar elements and not necessarily for describing a sequentialor chronological order. It is further understood that the terms so usedare interchangeable under appropriate circumstances such that theembodiments of the invention described herein are, for example, capableof operation in other sequences than illustrated or otherwise describedherein.

Moreover, the terms front, back, top, bottom, over, under, and the likein the description and in the claims, if any, are used for descriptivepurposes and not necessarily for describing permanent relativepositions. It is understood that the terms so used are interchangeableunder appropriate circumstances such that the embodiments of theinvention described herein are, for example, capable of operation inother orientations than illustrated or otherwise described herein.

DETAILED DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a partially schematic, cross-sectional view of asemiconductor component 100. As an example, semiconductor component 100can be electrically coupled to a forty-volt power supply (not shown inFIG. 1). Semiconductor component 100 comprises a semiconductor substrate110 having portions 111 and 112 with a first conductivity type. In thepreferred embodiment, the first conductivity type can be a P-typeconductivity. In an alternative embodiment, the first conductivity typecan be an N-type conductivity. As an example, portion 111 can be anepitaxial portion having a preferred thickness of less thanapproximately four micrometers. As a further example, portion 112 can bea substrate portion having a different doping concentration than portion111.

The semiconductor component also comprises a transistor 120 at leastpartially located in semiconductor substrate 110. Transistor 120 is ahigh power or high voltage transistor. As an example, transistor 120 canbe a MOS transistor or a Bipolar Junction Transistor (BJT) capable ofwithstanding approximately forty to one hundred volts across its drainand source terminals or its collector and emitter terminals. In theembodiment illustrated in FIG. 1, transistor 120 is a Laterally DiffusedMOS (LDMOS) transistor.

Transistor 120 is comprised of a doped region 121 in portion 111 ofsemiconductor substrate 110 and having the first conductivity type. Asan example, doped region 121 can also be referred to as a well regionfor transistor 120.

Transistor 120 also comprises a terminal 122 comprising an electrode 123and a doped region having a second conductivity type and located inportion 111 of semiconductor substrate 110 and over doped region 121. Inthe preferred embodiment, the second conductivity type can be an N-typeconductivity. In an alternative embodiment where the first conductivitytype is an N-type conductivity, the second conductivity type can be aP-type conductivity. In the embodiment illustrated in FIG. 1, terminal122 is a drain terminal for transistor 120. In a different embodimentwhere transistor 120 is a BJT, terminal 122 can be a collector terminal.

Also in the embodiment illustrated in FIG. 1, the doped region ofterminal 122 is comprised of doped regions 124 and 125. As an example,doped regions 124 and 125 can be referred to as a drift region and adrain region, respectively. In this embodiment, doped region 125 has ahigher doping concentration than doped regions 121 and 124.

Transistor 120 additionally comprises a doped region 126 having thesecond conductivity type and located in semiconductor substrate 110below portion 111 of semiconductor substrate 110 and above portion 112of semiconductor substrate 110. As an example, doped region 126 can belocated in a lower portion of portion 111 of semiconductor substrate 110and an upper portion of portion 112 of semiconductor substrate 110.Doped region 126 is comprised of doped regions 127 and 128. Doped region127 can be referred to as a buried layer or buried region. Doped region126 separates portion 111 of semiconductor substrate 110 from portion112 of semiconductor substrate 110. Doped region 126 can have a higherdoping concentration than doped regions 121 and 124 and a lower dopingconcentration than doped region 125.

Transistor 120 further comprises a terminal 129 comprising an electrode130 and a doped region 131 having the second conductivity type andlocated in portion 111 of semiconductor substrate 110 and over dopedregion 121. In the embodiment illustrated in FIG. 1, terminal 129 can bereferred to as a source terminal. In a different embodiment wheretransistor 120 is a BJT, terminal 129 can be referred to as an emitterterminal.

Transistor 120 still further comprises doped regions 132 and 133 havingthe first conductivity type. Doped region 133 can be referred to as abody region. As an example, doped region 132 can have a higher dopingconcentration than doped regions 121, 126, and 133.

Transistor 120 also comprises a terminal 134 comprising an electrode 135and an electrically insulative layer 136, both located over a topsurface of semiconductor substrate 110. In the embodiment illustrated inFIG. 1, terminal 134 can be referred to as a gate terminal. In adifferent embodiment where transistor 120 is a BJT, terminal 134 can bereferred to as a base terminal.

In the embodiment illustrated in FIG. 1, transistor 120 additionallycomprises an intrinsic BJT formed at least partially from doped regions121, 125, and 126. As an example, when terminal 122 is forward biasedwith respect to doped region 121, doped region 121 can be the baseregion of the intrinsic BJT; doped region 125 can be the emitter of theintrinsic BJT; and doped region 126 can be the collector of theintrinsic BJT. As another example, when terminal 122 is reverse biasedwith respect to doped region 121, doped region 121 can be the baseregion of the intrinsic BJT; doped region 125 can be the collector ofthe intrinsic BJT; and doped region 126 can be the emitter of theintrinsic BJT. The intrinsic BJT is active or turned-on when terminal122 is forward biased relative to doped region 121, and the intrinsicbipolar junction transistor is deactivated or turned-off when terminal122 is reverse biased relative to doped region 121. The activation anddeactivation of the intrinsic BJT are explained in more detailhereinafter.

In addition to semiconductor substrate 110 and transistor 120,semiconductor component 100 further comprises an integrated circuit 140at least partially located in semiconductor substrate 110 andelectrically coupled to transistor 120. Doped region 126 separates orisolates transistor 120 from integrated circuit 140.

Semiconductor component 100 still further comprises a switching circuit150 electrically coupled to doped region 126 to adjust the bias of dopedregion 126. Switching circuit 150 is illustrated in schematic form inFIG. 1. In a first embodiment, switching circuit 150 is at leastpartially located in semiconductor substrate 110. In a secondembodiment, switching circuit 150 is at least partially located oversemiconductor substrate 110. In a third embodiment, switching circuit150 is entirely located outside of semiconductor substrate 110.

Switching circuit 150 biases doped region 126 to prevent substrateinjection when doped region 125 is forward biased with respect to dopedregion 121 and to prevent punchthrough when doped region 125 isreverse-biased with respect to doped region 121. The use of switchingcircuit 150 eliminates the need for more costly and more complicatedepitaxial layers having higher doping concentrations towards dopedregion 127 to prevent punch-through between the doped region 125 anddoped region 126. The use of switching circuit 150 also eliminates theneed for thicker epitaxial layers, which are incompatible with industrygoals for thinner epitaxial layers, especially for fiber opticapplications.

Switching circuit 150 also biases doped region 126 to activate anddeactivate the intrinsic BJT in transistor 120. In the preferredembodiment, the biasing provided by switching circuit 150 is dynamicallyperformed during the operation of transistor 120.

For example, switching circuit 150 biases doped region 126 in adirection identical to a biasing direction of terminal 122 when terminal122 is reverse biased relative to doped region 121. In the preferredembodiment, such biasing of doped region 126 and terminal 122 occurssubstantially simultaneously. This biasing de-activates or turns off theintrinsic BJT in transistor 120.

As another example, switching circuit 150 biases doped region 126 atzero volts or reverse bias relative to portion 112 of semiconductorsubstrate 110 when terminal 122 is forward biased relative to dopedregion 121. In the preferred embodiment, such biasing of doped region126 and terminal 122 occurs substantially simultaneously. This biasingdeactivates or turns off the intrinsic BJT in transistor 120.

In the embodiment illustrated in FIG. 1, switching circuit 150 comprisesa single diode 160. As illustrated in FIG. 1, diode 160 is a P-N diodeand is electrically coupled to buried region 126. Diode 160 can be atleast partially located in semiconductor substrate 110. In thisembodiment, buried region 126 can be electrically floating.

When terminal 122 is forward biased with respect to doped region 121,the voltage of doped region 126 equals Vin, and the BJT is activated.When terminal 122 is reverse biased with respect to doped region 121 andis larger than Vin, the voltage of doped region 126 equals the voltageat terminal 122, and the intrinsic BJT is de-activated.

FIG. 2 illustrates a cross-sectional view of a semiconductor component200, which is an embodiment of semiconductor component 100 in FIG. 1.For simplicity, integrated circuit 140 in FIG. 1 is not illustrated inFIG. 2. Diode 160 in semiconductor component 200 in FIG. 2 comprises adoped region 261 in portion 111 of semiconductor substrate 110, a dopedregion 262 in portion 111 of semiconductor substrate 110, a portion ofportion 111 of semiconductor substrate 110, and doped region 126. Dopedregions 261 and 262 have the first conductivity type, and doped region261 has a higher doping concentration than doped region 262 and theportion of portion 111 of semiconductor substrate 110.

Diode 160 can be added to semiconductor component 200 without requiringany additional manufacturing steps. For example, doped region 261 can beformed simultaneously with doped region 132, and doped region 262 can beformed simultaneously with doped region 133.

FIG. 3 illustrates a partially schematic, cross-sectional view of asemiconductor component 300, which can be a different embodiment ofsemiconductor component 100 in FIG. 1. Similar to semiconductorcomponent 100 in FIG. 1, semiconductor component 300 in FIG. 3 comprisestransistor 120 and integrated circuit 140. For simplicity, integratedcircuit 140 in FIG. 1 is not illustrated in FIG. 3.

Semiconductor component 300 of FIG. 3 also comprises a switching circuit350. Switching circuit 350 comprises diodes 360 and 370. As illustratedin FIG. 3, diodes 360 and 370 are P-N diodes electrically coupled toeach other. As an example, diodes 360 and 370 can be configured in aback-to-back arrangement where diode 370 electrically couples togetherdoped region 125 and doped region 126 and where diode 360 electricallycouples together doped region 126 and an input voltage (Vin). Diodes 360and 370 can be at least partially located in semiconductor substrate110.

In operation, when the voltage applied to terminal 122 is greater thanthe input voltage, diode 370 is turned on, and diode 360 is turned off.Under these conditions, doped region 126 is approximately electricallyshorted or otherwise electrically coupled to terminal 122. Also underthese conditions, transistor 120 has a high drain-to-source breakdownvoltage. When the voltage applied to terminal 122 is less than the inputvoltage, diode 370 is turned off, and diode 360 is turned on. Underthese conditions, doped region 126 is not electrically shorted toterminal 122.

As an example, the input voltage can be offset from the voltage appliedto terminal 122 by approximately fifteen volts or less. Accordingly,diode 370 is preferably a high voltage diode, and diode 360 can be a lowvoltage diode. In the preferred embodiment where semiconductor component300 operates on a forty-volt power supply, the input voltage isapproximately one to five volts.

FIG. 4 illustrates a cross-sectional view of a semiconductor component400, which is an embodiment of semiconductor component 300 in FIG. 3.Diode 360 in semiconductor component 400 in FIG. 4 comprises a dopedregion 461 in portion 111 of semiconductor substrate 110, a doped region462 in portion 111 of semiconductor substrate 110, a portion of portion111 of semiconductor substrate 110, and doped region 126. Doped regions461 and 462 have the first conductivity type, and doped region 461 has ahigher doping concentration than doped region 462 and the portion ofportion 111 of semiconductor substrate 110. Diode 370 in semiconductorcomponent 400 comprises a doped region 471 and doped region 126. Dopedregion 471 has the first conductivity type. Preferably, doped region 462is separated from doped region 128 by approximately two to five microns.

Diodes 360 and 370 can be added to semiconductor component 400 withoutrequiring any additional manufacturing steps. For example, doped regions461 and 471 can be formed simultaneously with doped region 132, anddoped region 462 can be formed simultaneously with doped region 133.

Empirical results for a semiconductor component, such as semiconductorcomponent 400, have demonstrated that the back-to-back diode scheme ofdiodes 360 and 370 is fast enough to switch simultaneously withtransistor 120 to prevent premature breakdown within transistor 120.

FIG. 5 illustrates a cross-sectional view of a semiconductor component500, which is an embodiment of semiconductor component of FIG. 3. Inplace of diode 370 in semiconductor component 400 of FIG. 4,semiconductor component 500 in FIG. 5 comprises a diode 570 that is atleast partially formed in semiconductor substrate 110. Diode 570comprises doped regions 521, 571, 572, 573, and 574. Doped regions 521,571, and 572 have the first conductivity type, and doped regions 573 and574 have the second conductivity type. Doped regions 571 and 572 havehigher doping concentrations than doped region 521, and doped region 573has a higher doping concentration than doped region 574.

Diode 570 is formed from a BJT having its emitter terminal electricallycoupled to doped region 125 and having its base and collector terminalselectrically coupled to each other and to doped region 128. Theelectrical coupling together of the base and collector terminals todoped region 128 is facilitated by a doped region 575 of the secondconductivity type. The collector terminal for the BJT comprises dopedregions 571 and 521; the base terminal for the BJT comprises dopedregions 573 and 574; and the emitter terminal for the BJT comprisesdoped region 572.

Diode 570 also comprises doped regions 127, 128, and 528, whichelectrically isolate diode 570 from transistor 120. Diode 370 in FIG. 3is not electrically isolated from transistor 120 in semiconductorcomponent 300. Therefore, under certain conditions, diode 376 may injectundesirable minority carriers into transistor 120. This problem of diode370 in FIG. 3 is eliminated by diode 570 in FIG. 5. For semiconductorcomponent 500 in FIG. 5, doped region 126 can comprise doped regions127, 128, and 528.

Diode 570 can be added to semiconductor component 500 without requiringany additional manufacturing steps. For example, doped regions 571 and572 can be formed simultaneously with doped regions 132 and 461, anddoped regions 573 and 575 can be formed simultaneously with dopedregions 125 and 131. Additionally, doped region 574 can be formedsimultaneously with other base regions of other BJTs in the integratedcircuit of semiconductor component 500, and doped region 521 can beformed simultaneously with doped region 121. Furthermore, doped region528 can be formed simultaneously with doped region 128.

FIG. 6 illustrates a partially schematic, cross-sectional view of asemiconductor component 600, which can be a different embodiment ofsemiconductor component 100 in FIG. 1. Similar to semiconductorcomponent 100 in FIG. 1, semiconductor component 600 in FIG. 6 comprisestransistor 120 and integrated circuit 140. For simplicity, integratedcircuit 140 in FIG. 1 is not illustrated in FIG. 6.

Semiconductor component 600 of FIG. 6 also comprises a switching circuit650. Switching circuit 650 comprises a diode 660 and a resistor 670. Asillustrated in FIG. 6, diode 660 and resistor 670 are electricallycoupled to each other. As an example, diode 660 and resistor 670 can beconfigured such that resistor 670 electrically couples together terminal122 and doped region 126 and where diode 660 electrically couplestogether doped region 126 and an input voltage (Vin). Diode 660 andresistor 670 can be at least partially located in semiconductorsubstrate 110.

In operation, when the voltage applied to terminal 122 is greater thanthe input voltage, at least part of the voltage is dropped acrossresistor 670, and diode 660 is turned off. Under these conditions, dopedregion 126 is electrically coupled to terminal 122. Also under theseconditions, transistor 120 has a high drain-to-source breakdown voltage.When the voltage applied to terminal 122 is less than the input voltage,diode 660 is turned on. Under these conditions, doped region 126 is notelectrically shorted to terminal 122.

As an example, the input voltage can be offset from the voltage appliedto terminal 122 by approximately fifteen volts or less. Accordingly,resistor 670 preferably has a high resistance, and diode 660 can be alow voltage diode. In the preferred embodiment where semiconductorcomponent 600 operates on a forty-volt power supply, the input voltageis approximately one to five volts.

FIG. 7 illustrates a cross-sectional view of a semiconductor component700, which is an embodiment of semiconductor component 600 of FIG. 6.Diode 660 in semiconductor component 700 in FIG. 7 comprises a dopedregion 761 in portion 111 of semiconductor substrate 110, a doped region762 in portion 111 of semiconductor substrate 110, a portion of portion111 of semiconductor substrate 110, and doped region 126. Doped regions761 and 762 have the first conductivity type, and doped region 761 has ahigher doping concentration than doped region 762 and the portion ofportion 111 of semiconductor substrate 110. Preferably, doped region 762is separated from doped region 128 by approximately two to five microns.

Semiconductor component 700 also comprises a doped region 771 having thesecond conductivity type to facilitate the electrical coupling betweendoped region 126 and resistor 670. Resistor 670 in semiconductorcomponent 700 is preferably formed over the top surface of semiconductorsubstrate 110. Resistor 670 is also preferably comprised ofpolycrystalline silicon. In a different embodiment, resistor 670 can beformed at least partially within semiconductor substrate 110.

Diode 660 can be added to semiconductor component 700 without requiringany additional manufacturing steps. For example, doped region 761 can beformed simultaneously with doped region 132, and doped region 762 can beformed simultaneously with doped region 133. Furthermore, doped region771 can be formed simultaneously with doped regions 125 and 131.

FIG. 8 illustrates a partially schematic, cross-sectional view of asemiconductor component 800, which can be a different embodiment ofsemiconductor component 100 in FIG. 1. Similar to semiconductorcomponent 100 in FIG. 1, semiconductor component 800 in FIG. 8 comprisestransistor 120 and integrated circuit 140. For simplicity, integratedcircuit 140 in FIG. 1 is not illustrated in FIG. 8.

Semiconductor component 800 of FIG. 8 also comprises a switching circuit850. Switching circuit 850 comprises a diode 860, a resistor 870, and atransistor 880. As illustrated in FIG. 8, diode 860, resistor 870, andtransistor 880 are electrically coupled to each other. Diode 860,resistor 870, and transistor 880 can be at least partially located insemiconductor substrate 110.

For example, transistor 880 can be a BJT having an emitter terminal, abase terminal, and a collector terminal. Transistor 880 is electricallycoupled to doped region 126. As illustrated in FIG. 8, the emitterterminal of transistor 880 is electrically coupled to doped region 128of doped region 126.

As another example, diode 860 can be a Zener diode. Diode 860electrically couples terminal 122 to transistor 880 and resistor 870. Asillustrated in FIG. 8, diode 860 electrically couples doped region 125to the base terminal of transistor 880.

As a further example, resistor 870 can be a polycrystalline siliconresistor and can have a high resistance. Resistor 870 electricallycouples the collector terminal of transistor 880 to diode 860 and thebase terminal of transistor 880.

The voltage of doped region 126 equals the voltage of terminal 122 plusa voltage drop across the reverse-biased Zener diode minus a voltagedrop across the base to emitter of the transistor. For example, if thebase-to-emitter voltage equals approximately 0.7 volts and the dropacross diode 860 equals approximately 5 volts, then the voltage of dopedregion 126 is approximately 4.3 volts higher than voltage of terminal122. Hence, when terminal 122 is forward biased with respect to dopedregion 121, then the injected current from doped region 125 is collectedby doped region 126. Also, when terminal 122 is reverse biased withrespect to doped region 121, then the offset voltage between dopedregion 126 and terminal 122 causes the BJT to be de-activated orturned-off.

FIG. 9 illustrates a cross-sectional view of a semiconductor component900, which is an embodiment of semiconductor component 800 of FIG. 8.Transistor 880 in semiconductor component 900 comprises doped regions981, 982, 983, 984, 985, 986, 987, and 988. Doped regions 981 and 982have the first conductivity type, and doped regions 983, 984, 985, 986,987, and 988 have the second conductivity type. Doped region 981 has ahigher doping concentration than doped region 982, and doped regions 983and 985 have higher doping concentrations than doped regions 984, 986,987, and 988. Doped regions 986, 987, and 988 have higher dopingconcentrations than doped region 984.

As illustrated in FIG. 8, transistor 880 is a BJT with emitter,collector, and base terminals. The collector terminal for the BJTcomprises doped regions 984, 985, 986, 987, and 988; the base terminalfor the BJT comprises doped regions 981 and 982; and the emitterterminal for the BJT comprises doped region 983. The emitter terminal oftransistor 880 is electrically coupled to doped region 128, and thiselectrical coupling is facilitated by a doped region 989 of the secondconductivity type. Doped regions 986, 988, and 987 electrically isolatetransistor 880 from transistor 120.

Diode 860 comprises doped regions 961, 962, and 963. Doped regions 961and 962 have the second conductivity type, and doped region 963 has thefirst conductivity type. Doped region 961 has a higher dopingconcentration than doped region 962.

Diode 860 and transistor 880 can be added to semiconductor component 800without requiring any additional manufacturing steps. For example, dopedregions 961, 983, 985, and 989 can be formed simultaneously with dopedregions 125 and 131, and doped regions 963 and 981 can be formedsimultaneously with doped region 132. Additionally, doped regions 962,986, and 987 can be formed simultaneously with doped region 128, anddoped region 988 can be formed simultaneously with doped region 127.Furthermore, doped regions 982 and 984 can be formed simultaneously withother base and collector regions of other BJTs in the integrated circuitof semiconductor component 900.

FIG. 10 illustrates a flow chart 1000 of a method of operating asemiconductor component. As an example, the semiconductor component offlow chart 1000 can be similar to semiconductor components 100, 200,300, 400, 500, 600, 700, 800, and/or 900 in FIGS. 1, 2, 3, 4, 5, 6, 7,8, and 9, respectively. At a step 1010 of flow chart 1000 in FIG. 10, anintegrated circuit at least partially located in a semiconductorsubstrate is electrically biased. As an example, the integrated circuitcan be similar to integrated circuit 140 in FIG. 1.

At a step 1020 of flow chart 1000 in FIG. 10, a transistor at leastpartially located in the semiconductor substrate is electrically biased.As an example, the transistor can be similar to transistor 120 in FIGS.1, 2, 3, 4, 5, 6, 7, 8, and 9. In particular, the transistor in step1020 of FIG. 10 can comprise (1) a first doped region in a first portionof the semiconductor substrate and having a first conductivity type, (2)a terminal comprising a second doped region having a second conductivitytype and located in the first portion of the semiconductor substrate andover the first doped region, (3) a third doped region having the secondconductivity type, located in the semiconductor substrate below thefirst portion of the semiconductor substrate and above a second portionof the semiconductor substrate having the first conductivity type, andseparating the first portion of the semiconductor substrate from thesecond portion of the semiconductor substrate, and (4) an intrinsicbipolar junction transistor formed at least partially from the first,second, and third doped regions.

At a step 1030 of flow chart 1000 in FIG. 10, the intrinsic bipolarjunction transistor is deactivated when the drain terminal is reversebiased relative to the first doped region. As an example, the thirddoped region can be electrically biased to deactivate the intrinsicbipolar junction transistor. In particular, the third doped region canbe electrically biased in a direction identical to a biasing directionof the terminal when the terminal is reverse biased relative to thefirst doped region. Step 1030 of flow chart 1000 prevents or otherwisesuppresses the generation and injection of minority carriers into asubstrate portion or the second portion of the semiconductor substrate.

At a step 1040 of flow chart 1000 in FIG. 10, the intrinsic bipolarjunction transistor is activated when the drain terminal is forwardbiased relative to the first doped region. As an example, the thirddoped region can be electrically biased to activate the intrinsicbipolar junction transistor. In particular, the third doped region canbe electrically biased at zero volts or reverse bias relative to thesecond portion of the semiconductor substrate when the terminal isforward biased relative to the first doped region. Step 1040 of flowchart 1000 enables the transistor of step 1020 to have a highdrain-to-source breakdown voltage.

In general, steps 1020 and 1030 of flow chart 1000 prevent punch-throughbetween the second doped region and the third doped region of thetransistor. One skilled in the art will understand that the sequence ofsteps in flow chart 1000 can be altered in many different ways. Forexample, step 1030 can be performed before step 1020. Additionally,steps 1010, 1020, and 1030 can be performed simultaneously with eachother; and steps 1010, 1020, and 1040 can be performed simultaneouslywith each other.

Therefore, an improved semiconductor component and method of operationis provided to overcome the disadvantages of the prior art. For example,the semiconductor component has a power transistor combined with anintegrated circuit onto a single semiconductor substrate where the powertransistor has a high drain-to-source breakdown voltage and iselectrically isolated from the integrated circuit. The semiconductorsubstrate can comprise a thin epitaxial semiconductor layer, in whichthe power transistor and the integrated circuit are formed. A method ofoperating a semiconductor component also suppresses the injection ofminority carriers into the semiconductor substrate.

Although the invention has been described with reference to specificembodiments, it will be understood by those skilled in the art thatvarious changes may be made without departing from the spirit or scopeof the invention. For instance, the numerous details set forth hereinsuch as, for example, the dimensions, the relative dopingconcentrations, and the specific diodes, resistors, and transistors usedin the switching circuits are provided to facilitate the understandingof the invention and are not provided to limit the scope of theinvention. As an example, the diodes in the switching circuits can beSchottky diodes, and the resistors in the switching circuits can becrystalline silicon diodes formed in the semiconductor substrate.Accordingly, the disclosure of embodiments of the invention is intendedto be illustrative of the scope of the invention and is not intended tobe limiting. It is intended that the scope of the invention shall belimited only to the extent required by the appended claims.

Benefits, other advantages, and solutions to problems have beendescribed with regard to specific embodiments. The benefits, advantages,solutions to problems, and any element or elements that may cause anybenefit, advantage, or solution to occur or become more pronounced,however, are not to be construed as critical, required, or essentialfeatures or elements of any or all of the claims. As used herein, theterm “comprise,” “include,” “have,” and any variations thereof, areintended to cover a non-exclusive inclusion, such that a process,method, article, or apparatus that comprises a list of elements does notinclude only those elements, but may include other elements notexpressly listed or inherent to such process, method, article, orapparatus.

What is claimed is:
 1. A semiconductor component comprising: a semiconductor substrate having first and second portions with a first conductivity type; a transistor at least partially located in the semiconductor substrate and comprising: a first doped region in the first portion of the semiconductor substrate and having the first conductivity type; a first terminal comprising a second doped region having a second conductivity type and located in the first portion of the semiconductor substrate and over the first doped region; and a third doped region having the second conductivity type and located in the semiconductor substrate below the first portion of the semiconductor substrate and above the second portion of the semiconductor substrate; a fourth doped region having the first conductivity type formed within the first doped region and electrically coupled to the first doped region; a second terminal electrically coupled to the fourth doped region for providing a bias to the fourth doped region and the first doped region; and a switching circuit electrically coupled to the third doped region to adjust a bias of the third doped region, wherein: the third doped region separates the first portion of the semiconductor substrate from the second portion of the semiconductor substrate.
 2. The semiconductor component of claim 1 wherein: the switching circuit biases the third doped region to prevent punch-through between the second and third doped regions.
 3. The semiconductor component of claim 1 wherein: the switching circuit forward biases the third doped region and the first terminal when the first terminal is reverse biased relative to the first doped region.
 4. The semiconductor component of claim 1 wherein: the switching circuit biases the third doped region at zero volts or reverse bias relative to the second portion of the semiconductor substrate when the first terminal is forward biased relative to the first doped region.
 5. The semiconductor component of claim 1 wherein: the transistor further comprises: an intrinsic bipolar junction transistor formed at least partially from the first, second, and third doped regions; the intrinsic bipolar junction transistor is active when the first terminal is forward biased relative to the first doped region; and the switching circuit deactivates the intrinsic bipolar junction transistor when the first terminal is reverse biased relative to the first doped region.
 6. The semiconductor component of claim 1 wherein: the switching circuit is at least partially located in the semiconductor substrate.
 7. The semiconductor component of claim 1 wherein: the switching circuit is at least partially located over the semiconductor substrate.
 8. The semiconductor component of claim 1 wherein: the switching circuit is entirely located outside of the semiconductor substrate.
 9. The semiconductor component of claim 1 wherein: the switching circuit comprises a single diode.
 10. The semiconductor component of claim 1 wherein: the switching circuit comprises two diodes.
 11. A semiconductor component comprising: a semiconductor substrate having first and second portions with a first conductivity type; a transistor at least partially located in the semiconductor substrate and comprising: a first doped region in the first portion of the semiconductor substrate and having the first conductivity type; a terminal comprising a second doped region having a second conductivity type and located in the first portion of the semiconductor substrate and over the first doped region; and a third doped region having the second conductivity type and located in the semiconductor substrate below the first portion of the semiconductor substrate and above the second portion of the semiconductor substrate; and a switching circuit electrically coupled to the third doped region to adjust a bias of the third doped region, wherein: the third doped region separates the first portion of the semiconductor substrate from the second portion of the semiconductor substrate; and the switching circuit comprises a single diode.
 12. A semiconductor component comprising: a semiconductor substrate having first and second portions with a first conductivity type; a transistor at least partially located in the semiconductor substrate and comprising: a first doped region in the first portion of the semiconductor substrate and having the first conductivity type; a terminal comprising a second doped region having a second conductivity type and located in the first portion of the semiconductor substrate and over the first doped region; and a third doped region having the second conductivity type and located in the semiconductor substrate below the first portion of the semiconductor substrate and above the second portion of the semiconductor substrate; and a switching circuit electrically coupled to the third doped region to adjust a bias of the third doped region, wherein: the third doped region separates the first portion of the semiconductor substrate from the second portion of the semiconductor substrate; and the switching circuit comprises two diodes.
 13. A semiconductor component comprising: a semiconductor substrate having first and second portions with a first conductivity type; a transistor at least partially located in the semiconductor substrate and comprising: a first doped region in the first portion of the semiconductor substrate and having the first conductivity type; a terminal comprising a second doped region having a second conductivity type and located in the first portion of the semiconductor substrate and over the first doped region; and a third doped region having the second conductivity type and located in the semiconductor substrate below the first portion of the semiconductor substrate and above the second portion of the semiconductor substrate; and a switching circuit electrically coupled to the third doped region to adjust a bias of the third doped region, wherein: the third doped region separates the first portion of the semiconductor substrate from the second portion of the semiconductor substrate; and the switching circuit comprises a bipolar junction transistor, a diode, and a resistor.
 14. A semiconductor component comprising: a semiconductor substrate having first and second portions with a first conductivity type; a transistor at least partially located in the semiconductor substrate and comprising: a first doped region in the first portion of the semiconductor substrate and having the first conductivity type; a terminal comprising a second doped region having a second conductivity type and located in the first portion of the semiconductor substrate and over the first doped region; and a third doped region having the second conductivity type and located in the semiconductor substrate below the first portion of the semiconductor substrate and above the second portion of the semiconductor substrate; and a switching circuit electrically coupled to the third doped region to adjust a bias of the third doped region, wherein: the third doped region separates the first portion of the semiconductor substrate from the second portion of the semiconductor substrate; and the switching circuit comprises a resistor and a diode.
 15. The semiconductor component of claim 11 wherein: the two diodes are configured in a back-to-back arrangement.
 16. The semiconductor component of claim 11 wherein: a first one of the two diodes electrically couples together the second doped region and the third doped region; and a second one of the two diodes electrically couples together the third doped region and an input voltage.
 17. The semiconductor component of claim 1 wherein: the switching circuit comprises: a bipolar junction transistor; a diode; and a resistor.
 18. The semiconductor component of claim 13 wherein: the diode is a Zener diode and electrically couples the second doped region to the bipolar junction transistor and the resistor; and the bipolar junction transistor is electrically coupled to the third doped region.
 19. The semiconductor component of claim 1 wherein: the switching circuit comprises: a resistor; and a diode.
 20. The semiconductor component of claim 14 wherein: the resistor electrically couples together the second and third doped regions; and the diode is electrically coupled to the third doped region and an input voltage.
 21. A semiconductor component comprising: a semiconductor substrate having a substrate portion with a first conductivity type and an epitaxial portion with the first conductivity type; a MOS transistor at least partially located in the semiconductor substrate and comprising: a well region in the epitaxial portion of the semiconductor substrate and having the first conductivity type; a drain terminal comprising a drain region having a second conductivity type and located in the epitaxial portion of the semiconductor substrate and over the well region; and a buried region having the second conductivity type and located in the semiconductor substrate below the epitaxial portion of the semiconductor substrate and above the substrate portion of the semiconductor substrate; a switching circuit at least partially located in the epitaxial portion of the semiconductor substrate and electrically coupled to the buried region to adjust a bias of the buried region; and an integrated circuit at least partially located in the semiconductor substrate and electrically coupled to the MOS transistor, wherein: the buried region separates the epitaxial portion of the semiconductor substrate from the substrate portion of the semiconductor substrate.
 22. The semiconductor component of claim 21 wherein: the switching circuit biases the buried region to prevent punch-through between the drain region and the buried region; the switching circuit substantially simultaneously biases the buried region in a direction identical to a biasing direction of the drain terminal when the drain terminal is reverse biased relative to the well region; and the switching circuit substantially simultaneously biases the buried region at zero volts or reverse bias relative to the substrate portion of the semiconductor substrate when the drain terminal is forward biased relative to the well region.
 23. The semiconductor component of claim 21 wherein: the MOS transistor further comprises: an intrinsic bipolar junction transistor formed at least partially from the drain region, the buried region, and the well region; the intrinsic bipolar junction transistor is active when the drain terminal is forward biased relative to the well region; and the switching circuit deactivates the intrinsic bipolar junction transistor when the drain terminal is reverse biased relative to the well region.
 24. The semiconductor component of claim 21 wherein: the switching circuit consists of a P-N diode at least partially located in the semiconductor substrate and electrically coupled to the buried region.
 25. The semiconductor component of claim 21 wherein: the switching circuit comprises two P-N diodes at least partially located in the semiconductor substrate and configured in a back-to-back arrangement; a first one of the two P-N diodes electrically couples together the drain region and the buried region; and a second one of the two P-N diodes electrically couples together the buried region and an input voltage.
 26. The semiconductor component of claim 21 wherein: the switching circuit comprises: a bipolar junction transistor at least partially located in the semiconductor substrate and comprising an emitter terminal, a base terminal, and a collector terminal; a Zener diode at least partially located in the semiconductor substrate and electrically coupling together the drain terminal and the base terminal; and a resistor electrically coupling the collector terminal to the base terminal and the Zener diode.
 27. The semiconductor component of claim 21 wherein: the switching circuit comprises: a resistor electrically coupling together the drain terminal and the buried region; and a diode at least partially located in the semiconductor substrate and electrically coupled to the buried region and the resistor. 